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integrated silicon solution, inc. 1 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams august 2010 features ? ? ? ? ? ? ? ? ? 2 m x 36 or 4 m x 18. on-chip delay-locked loop (dll) for wide data valid window. common data input/output bus. synchronous pipeline read with self-timed late write operation. d ou ble d ata r ate (ddr -iip ) i nt erf ace f or re a d a nd write input ports. fixed 2-bit burst for read and write operations. clock stop support. two input clocks (k and k ) for address and con- trol registering at rising edges only. industrial temperature available upon request. two echo clocks (cq and cq ) that are delivered simultaneously with data. +1.8v core power supply and 1.5, 1.8v v ddq , used with 0.75, 0.9v v ref . hstl input and output levels. registered addresses, write and read controls, byte writes, data in, and data outputs. full data coherency. boundary scan using limited set of jtag 1149.1 functions. byte write capability. fine ball grid array (fbga) package - 15mm x 17mm body size - 1mm pitch - 165-ball (11 x 15) array programmable impedance output drivers via 5x user-supplied precision resistor. description the 72 mb is61ddpb22m36 and is61ddpb24m18 are s ynchr onous , h igh-pe rfor - mance cmos static random access memory (sram) devices. these srams have a common i/o bus. the rising edge of k clock initiates the read/write operation, and all internal operations are self-timed. refer to the timing reference diagram for truth tabl e on page 8 f or a description of the basi c opera- ti ons of these ddr-iip (burst of 2) cio sr a ms . the input addresses are registered on all rising edges of the k clock. the dq bus operates at double data rate for reads and writes. the following are registered internally on the rising edge of the k clock: read and write addresses address load read/write enable b y te data-in the following are registered on the rising edge of the k clock: data-in for second burst addresses byte writes can change with the corresponding data- in to enable or disable writes on a per-byte basis. an internal write buffer enables the data-ins to be regis- tered one cycle later than the write address. the first data-in burst is clocked with the rising edge of the next k clock, and the second burst is timed to the following rising edge of the k clock. during the burst read operation, at the first burst the data-outs are updated from output registers off the second rising edge of the k clock ( 2 .5 cycles later). at the second burst, the data-outs are updated with the fourth rising edge of the correspon ding k clock (see page 8 ). the device is operated with a si ngle +1.8v power supply and is compatible with hstl i/o interfaces. . writes b y te writes (2.5 cycle read latency) data-out ? ? ?? ? ? data-out ? ? ? ? ? ? ? ? ? ? ? ?
2 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d x36 fbga pinout (top view) 1234567891011 acq nc /sa* sa r/w bw 2 k bw 1 ld sa sa cq b nc dq27 dq18 sa bw 3 kbw 0 sa nc nc dq8 cnc ncdq28v ss sa nc sa v ss nc dq17 dq7 dncdq29dq19v ss v ss v ss v ss v ss nc nc dq16 enc ncdq20v ddq v ss v ss v ss v ddq nc dq15 dq6 f nc dq30 dq21 v ddq v dd v ss v dd v ddq nc nc dq5 g nc dq31 dq22 v ddq v dd v ss v dd v ddq nc nc dq14 hdoff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq jnc ncdq32v ddq v dd v ss v dd v ddq nc dq13 dq4 knc ncdq23v ddq v dd v ss v dd v ddq nc dq12 dq3 l nc dq33 dq24 v ddq v ss v ss v ss v ddq nc nc dq2 mnc ncdq34v ss v ss v ss v ss v ss nc dq11 dq1 nncdq35dq25v ss sa sa sa v ss nc nc dq10 p nc nc dq26 sa sa nc nc sa sa nc dq9 dq0 rtdotcksasasa sa sa sa tms tdi * the following pins are reserved for higher densities: 2a for 144mb bw 0 controls writes to dq0?dq8; bw 1 controls writes to dq9?dq17; bw 2 controls writes to dq18?dq26; bw 3 controls writes to dq27?dq35. x18 fbga pinout (top view) 1234567891011 acq sa sa r/w bw 1 k nc/sa * ld sa sa cq b nc dq9 nc sa nc/sa * k bw 0 sa nc nc dq8 cnc nc nc v ss sa nc sa v ss nc dq7 nc dnc ncdq10v ss v ss v ss v ss v ss nc nc nc enc ncdq11v ddq v ss v ss v ss v ddq nc nc dq6 fncdq12ncv ddq v dd v ss v dd v ddq nc nc dq5 gnc ncdq13v ddq v dd v ss v dd v ddq nc nc nc hdoff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq jnc nc ncv ddq v dd v ss v dd v ddq nc dq4 nc knc ncdq14v ddq v dd v ss v dd v ddq nc nc dq3 lncdq15ncv ddq v ss v ss v ss v ddq nc nc dq2 mnc nc nc v ss v ss v ss v ss v ss nc dq1 nc nnc ncdq16v ss sa sa sa v ss nc nc nc p nc nc dq17 sa sa nc nc sa sa nc nc dq0 rtdotcksasasa sa sa sa tms tdi * the following pin is reserved for higher densities: 7a for 144mb, 5b for 288mb. bw 0 controls writes to dq0?dq8; bw 1 controls writes to dq9?dq17 ? ?
integrated silicon solution, inc. 3 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams d i 3 d pin description symbol pin number description k, k 6b, 6a input clock. cq, cq 11a, 1a output echo clock. doff 1h dll disable when low. sa 3a, 9a, 10a, 4b, 8b, 5c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4r, 5r, 7r,8 r, 9r 2 m x 36 address inputs. sa 2a, 3 a, 9a, 10a, 4b, 8b, 5c, 7c, 5n, 6n, 7n, 4p, 5p, 7p, 8p, 3r, 4 r, 5 r, 7r, 8r, 9r 4 m x 18 address inputs. dq0?dq8 dq9?dq17 dq18?dq26 dq27?dq35 11p, 11m, 11l, 11k, 11j, 11f, 11e, 11c, 11b 10p, 11n, 10m, 10k, 10j, 11g, 10e, 11d, 10c 3b, 3d, 3e, 3f, 3g, 3k, 3l, 3n, 3p 2b, 3c, 2d, 2f, 2g, 3j, 2l, 3m, 2n 2m x 36 dq pins dq0?dq8 dq9?dq17 11p, 10m, 11l, 11k, 10j, 11f, 11e, 10c, 11b 2b, 3d, 3e, 2f, 3g, 3k, 2l, 3n, 3p 4m x 18 dq pins r/w 4a read/write control. read when active high. ld 8a synchronizes load. loads new address when low. bw 0, bw 1, bw 2, bw 3 7b, 7a, 5a,5b 2m x 36 byte write control, active low. bw 0, bw 1 7b, 5a 4m x 18 byte write control, active low. v ref 2h, 10h input reference level. v dd 5f, 7f, 5g, 7g, 5h, 7h, 5j, 7j, 5k, 7k power supply. v ddq 4e,8e,4f,8f,4g,8g,3h,4h,8h,9h,4j,8j,4k,8k,4l,8l output power supply. v ss 4c, 8c, 4d, 5d, 6d, 7d, 8d, 5e, 6e, 7e, 6f, 6g, 6h, 6j, 6k, 5l, 6l, 7l, 4m, 5m, 6m, 7m, 8m, 4n, 8n ground zq 11h output driver impedance control. tms, tdi, tck 10r, 11r, 2r ieee 1149.1 test inputs (1.8v lvttl lev- els). t nc nc 2a, 1b, 9b, 10b, 1c, 2c, 9c, 1d, 9d, 10d, 1e, 2e, 9e, 1f, 9f, 10f, 1g, 9g, 10g, 1j, 2j, 9j, 1k, 2k, 9k, 1l, 9l, 10l, 1m, 2m, 9m, 1n, 9n, 10n, 1p, 2p, 9p, 6r, 6p, 6c 7a, 1b, 3b, 5b, 9b, 10b, 1c, 2c, 3c, 9c, 11c, 1d, 2d, 9d, 10d, 11d, 1e, 2e, 9e, 10e, 1f, 3f, 9f, 10f, 1g, 2g, 9g, 10g, 11g, 1j, 2j, 3j, 9j, 11j, 1k, 2k, 9k, 10k, 1l, 3l, 9l, 10l, 1m, 2m, 3m, 9m, 11m, 1n, 2n, 9n, 10n, 11n, 1p, 2p, 9p, 10p, 6r, 6p, 6c x36 configuration x18 configuration do 1r ieee 1149.1 test output (1.8v lvttl level).
4 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d block diagram 2m x 36 (4 m x 18) memory array write/read decode sense amps write driver select output control data reg add reg & control logic clock gen output reg output select output driver 36 (or 18) 72 (or 36) 36 (or 18) dq (data-out cq, cq (echo clock out) address ld r/w bw x k k d off 4 (or 2) 20 (or 2 1 ) 20 (or 2 1 ) 36 (or 18) & data-in) a0 burst control 36 (or 18) sram features read operations the sram operates continuously in a burst-of-two mode. read cycles are started by registering r/ w in active high state at the rising edge of the k clock. the k and k clocks are also used to control the timing to the outputs. the data corresponding to the first address is clocked 2.5 cycles later by the rising edge of the k clock. the data corresponding to the second burst is cloc ked 3 cycles later by the following rising edge of the k clock. a set of free-running echo clocks, cq and cq , are produced internally with timings identical to the data-outs. the echo clocks can be used as data capture clocks by the receiver device. whenever ld is low, a new address is registered at the rising edge of the k clock. a nop operation ( ld is high) does not terminate the previous read. the output drivers disable automatically to a high state. write operations write operations can also be initiated at every rising edge of the k clock whenever r/ w is low. the write address is also registered at that ti me. when the address needs to change, ld needs to be low simultaneously to be registered by the rising edge of k. again, the write always occurs in bursts of two. because of its common i/o architectu re, the data bus must be tri-stated at least one cycle before the new data-in is presented at the dq bus. the write data is provided in a ?late write? mode; that is, the data-in co rresponding to the first address of the burst, is presented one cycle later or at the rising edge of the next k clock. the data-in corresponding to the second write burst address follows next, registered by the rising edge of k.
integrated silicon solution, inc. 5 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams 72 mb (2m x 36 & 4m x 18) ddr-ii (burst of 2) cio synchronous srams i 3 d the data-in provided for writing is initially kept in write buffers. the information on these buffers is written into the array on the following write cycle. a read cycle to the last write address produces data from the write buffers. similarly, a read address followed by the same write address produces the latest write data. the sram maintains data coherency. during a write, the byte writes independently control which byte of any of the two burst addresses is written (see x18/x36 wri te truth tabl es on page 9 and t i ming referen ce di agram for truth tabl e on p age 8). whenever a write is disabled (r/w is high at the rising edge of k), data is not written into the memory. rq programmable impedance an external resistor, rq, must be connected between the zq pin on the sram and v ss to enable the sram to adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. for example, an rq of 250 ? results in a driver impedance of 50 ? . the allowable range of rq to guarantee impedance matching is between 175 ? and 350 ? , with the tolerance described in programmable impedance output driver dc electrical characteristics on page 1 3 . the rq resistor should be placed less than two inches away from the zq ball on the sram module. the capacitance of the loaded zq trace must be less than 3 pf. the zq pin can also be directly connected to v ddq to obtain a minimum impedance setting. zq must never be connected to v ss . programmable impedance and power-up requirements periodic readjustment of the output driver impedance is necessary as the impedance is greatly affected by drifts in supply voltage and temperature. at power-up, the driver impedance is in the middle of allowable impedances values. the final impedance value is achieved within 2048 clock cycles.
6 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams app licati on e xa mple sa ld r/w bw 0 bw 1 k k dq 0?17 zq sram #4 r =2 50 vt data-i n/d ata-out ad dre ss ld r/w bw m em ory controller sou rce clk sou rce clk sa ld r/w bw 0 bw 1 k k dq 0?17 zq cq/ cq cq/ cq sram #1 r =2 50 vt r r=50 vt=v ref r e cho clo ck e cho clo ck the following figure depicts an implementation of four 4m x 18 ddr-iip srams with common i/os. power-up and power-down sequences the following sequence is used for power-up: 1. the power supply inputs must be applied in the following order while keeping doff in low logic state: 1) vdd 2) vddq 3) vref 2. start applying stable clock inputs (k, k, c, and c). 3. after clock signals have stabilized, change doff to high logic state. 4. once the doff is switched to high logic state, wait an additional 1024 clock cycles to lock the dll. notes: 1. the power-down sequence must be done in reverse of the power-up sequence. 2. vddq can be allowed to exceed vdd by no more than 0.6v. 3. vref can be applied concurrently with vddq.
integrated silicon solution, inc. 7 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams 72 mb (2m x 36 & 4m x 18) ddr-ii (burst of 2) cio synchronous srams i 3 d the ti ming re fe rence di agra m for truth tabl e on page 8 is hel p ful i n u nd ersta n di n g t h e c l o ck and w rite t rut h tables, as it shows the cycle relationship between clocks, address, data in, data out, and controls. all read and write commands are issued at the beginning of cycle ?t?. state diagram linear burst sequence table burst sequence sa 0 first address 1 second address 0 power up ddr -iip write nop ddr -ii p read write write notes: 1. read refers to read active status with r/w = high. 3. load refers to read new address active status with ld = low. 2. write refers to write active status with r/w = low. load new address load load read load load load load 4. load is read new address inactive status with ld = high.
8 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d timing reference diagram for truth table clock truth table (use the following table with the timing reference diagram for truth table .) mode clock controls data-out/data-in kl d r/w q a / d b q a+1 / d b+1 stop clock stop x x previous state previous state no operation (nop) l h h h high-z high-z read a l h l x d out at k (t + 2.5) d out at k (t + 3) write b l hx l d b (t w + 1) d b (t w + 1.5) notes : 1. the internal burst counter is always fixed as two-bit. 2. x = don?t care; h = logic ?1?; l = logic ?0?. 3. a read operation is started when control signal r/w is active high. 4. a write operation is started when control signal r/w is active low. 5. before entering into the stop clock, all pending read and write commands must be completed. 6. for timing defin ition s, refer to t he ac characte r ist i cs on page 15 . signals must h ave ac speci fications at timi ngs indicated i n parenthesis with respect to switching clocks k and k . tt + 1t + 2 nop a qa +1 k clock k clock ld r / w bw 0,1,2,3 address data-in/ cq clock cq clock cycle t w t w+1 db nop read a b w write b rite b data-out (dq) t+3 t+2.5 qa
integrated silicon solution, inc. 9 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams 3 d x36 write truth table use the following table with the timing reference diagram for truth table on page 8. operation k (t w ) k (t w + 0.5) bw 0 bw 1 bw 2 bw 3 d b d b+1 write byte 0 l h l h h h d0-8 (t w + 1) write byte 1 l h h l h h d9-17 (t w + 1) write byte 2 l h h h l h d18-26 (t w + 1) write byte 3 l h h h h l d27-35 (t w + 1) write all bytes l h l l l l d0-35 (t w + 1) abort write l h h h h h don?t care write byte 0 l h l h h h d0-8 (t w + 1.5) write byte 1 l h h l h h d9-17 (t w+1.5 ) write byte 2 l h h h l h d18-26 (t w+1.5 ) write byte 3 l hhhhl d27-35 (t w+1.5 ) write all bytes l h l l l l d0-35 (t w+1.5 ) abort write l hhhhh don?t care notes ; 1. for all cases. r/w must be active low during the rising edge of k occurring at time t w . 2. for timing defini tions, re fer to the ac characte r istics on page 15. signals must h a ve a c s pecifications with respect t o s witching clocks k and k . x18 write truth tab le (use this table with the t i m i ng referen ce di agram for truth table o n page 8.) operation k (t w ) k (t w+0.5 ) bw 0 bw 1 d b d b+1 write byte 0 on b l h l h d0-8 (t w + 1) write byte 1 on b l h h l d9?17 (t w + 1) write all bytes on b l h l l d0?17 (t w + 1) abort write on b l h h h don?t care write byte 1 on b+1 l h l h d0?8 (t w + 1.5) write byte 2 on b+1 l h h l d9?17 (t w + 1.5) write all bytes on b+1 l h l l d0?17 (t w + 1.5) abort write on b+1 l h h h don?t care notes ; 1. r ef e r to timing reference diagram for truth t abl e on page 8. cycle time starts at n and is referenced to t he k clock. 2. for all cases, r/w must be active low during the rising edge of k occurring at t w . 3. for timing defini tions, refer t o the a c characte risti cs on page 15. signals must ha ve ac specs wi t h respe ct t o switching clocks k and k .
10 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d absolute maximum ratings item symbol rating units power supply voltage v dd -0.5 to 2. 9 v output power supply voltage v ddq -0.5 to 2. 9 v input voltage v in -0.5 to vdd+0.3 v data out voltage v dout -0.5 to 2.6 v operating temperature t a 0 to 70 c junction temperature t j 110 c storage temperature t stg -55 to +125 c note: stresses greater than those listed in this table can cause permanent damage to the device. this is a stress rating only and fun c- tional operation of the device at these or any other conditions above those indicated in the operational sections of this datas heet is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability.
integrated silicon solution, inc. 11 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d recommended dc operating conditions (t a = 0 to + 70 c) parameter symbol minimum typical maximum units notes supply voltage v dd 1.8 - 5% 1.8 + 5% v 1 output driver supply voltage v ddq 1.4 1.9 v 1 input high voltage v ih v ref +0.1 v ddq + 0.2 v 1, 2 input low voltage v il -0.2 v ref - 0.1 v 1, 3 input reference voltage v ref 0.68 0.95 v 1, 5 clocks signal voltage v in - clk -0.2 v ddq + 0.2 v 1, 4 1. all voltages are referenced to v ss . all v dd , v ddq , and v ss pins must be connected. 2. v ih (max) ac = see 0vershoot and undershoot timings . 3. v il (min) ac = see 0vershoot and undershoot timings . 4. v in-clk specifies the maximum allowable dc excursions of each clock (k and k ). 5. peak-to-peak ac component superimposed on v ref may not exceed 5% of v ref. 0vershoot and undershoot timings pbga thermal characteristics item symbol rating units thermal resistance junction to ambient (airflow = 1m/s) r ja tbd c/w thermal resistance junction to case r jc tbd c/w thermal resistance junction to pins r jb tbd c/w v ddq 20% min cycle time v ddq +0.6v gnd-0.6v gnd 20% min cycle time overshoot timing undershoot timing v ih (max) ac v il (min) ac
12 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d capacitance (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%, f = 1mhz) parameter symbol test condition maximum units input capacitance c in v in = 0v 4 pf data-in/out capacitance (dq0?dq35) c dq v din = 0v 4 pf clocks capacitance (k and k )c clk v clk = 0v 4 pf dc electrical characteristics (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%) parameter symbol minimum maximum units notes x36 average power supply operating current (i out = 0, v in = v ih or v il ) i dd3 3 i dd40 i dd50 i dd3 3 i dd40 i dd50 ma 1, 3 x18 average power supply operating current (i out = 0, v in = v ih or v il ) ma 1, 3 power supply standby current (r = v ih , w = v ih . all other inputs = v ih or v ih , i ih = 0) i sbss ? ma 1 input leakage current, any input (except jtag) (v in = v ss or v dd ) i li -2 +2 output leakage current (v out = v ss or v ddq , q in high-z) i lo -2 +2 output ?high? level voltage (i oh = -6ma) v oh v ddq -.4 v ddq v output ?low? level voltage (i ol = +6ma) v ol v ss v ss +.4 v 2, 4 jtag leakage current (v in = v ss or v dd ) i lijtag -100 +100 1. i out = chip output current. 2. minimum impedance output driver. 3. the numeric su ffix indicates the part opera ting at speed, as indicated in ac characte rist ics o n page 15. 2 4. jedec standard jesd8-6 class 1 compatible. 5. for jtag inputs only. 6. currents are estimates only and need to be verified. 2, 4 ua ua ua 5 200 600 550 500 600 550 500 ? ? ? ? ? ?
integrated silicon solution, inc. 13 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d typical ac input characteristics item symbol minimum maximum notes ac input logic high v ih (ac) v ref + 0. 2 1, 2, 3, 4 ac input logic low v il (ac) v ref - 0. 2 1, 2, 3, 4 clock input logic high (k, k ) v ih-clk (ac) v ref + 0. 2 1, 2, 3 clock input logic low (k, k ) v il-clk (ac) v ref - 0. 2 1, 2, 3 1. the peak-to-peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. performance is a function of v ih and v il levels to clock inputs. 3. see the ac input definition diagram. 4. see the ac input definition diagram. the signals should swing monotonically with no steps rail-to-rail with input signals never ring- ing back past vih (ac) and vil (ac) during the input setup and input hold window. vih (ac) and vil (ac) are used for timing pur - poses only. ac input definition programmable impedance output driver dc electrical characteristics (t a = 0 to +70 c, v dd = 1.8v -5%, +5%, v ddq = 1.5, 1.8v) parameter symbol minimum maximum units notes output ?high? level voltage v oh v ddq / 2 v ddq v1, 3 output ?low? level voltage v ol v ss v ddq / 2 v 2, 3 1. i oh = 15% @ v oh = v ddq / 2 for: 175 ? rq 350 ? . 2. i ol = 15% @ v ol = v ddq / 2 for: 175 ? rq 350 ? . 3. parameter tested with rq = 250 ? and v ddq = 1.5v. v ih (ac) v ref v il (ac) setup time hold time v ref k k v rail v -rail vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ? vddq 2 ------------------ ?? ?? rq 5 -------- ? ? ? ? ?
14 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d ac test conditions (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%, v ddq = 1.5, 1.8v) parameter symbol conditions units notes output driver supply voltage v ddq 1.5, 1.8 v input high level v ih v ref +0.5 v input low level v il v ref -0.5 v input reference voltage v ref 0.75, 0.9 v input rise time t r 0.35 ns input fall time t f 0.35 ns output timing reference level v ref v clocks reference level v ref v output load conditions 1, 2 1. see ac test loading . 2. parameter tested with rq = 250 ? and v ddq = 1.5v. ac test loading q 50 ? 50 ? 5pf 0.75, 0.9v 0.75, 0.9v test comparator
integrated silicon solution, inc. 15 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams ac characteristics (vdd = 1.8v + 0.1v, t a = 0 oc to 70 oc) issi parameter description ddr iip 400 375 333 300 unit notes min max min max min max min max tkhkh k clock cycle time 2.50 7.50 2.66 7.50 3.00 7.50 3.30 7.50 ns tkhkl input clock (k/k) high 0.40 0.40 0.40 0.40 tkhkh tklkh input clock (k/k) low 0.40 0.40 0.40 0.40 tkhkh tkhkh k clock rise to k clock rise (rising edge to rising edge) 1.06 1.13 1.28 1.40 ns setup times tavkh address setup to k clock rise 0.40 0.40 0.40 0.40 ns 2 tivkh control setup to k clock rise (r, w) 0.40 0.40 0.40 0.40 ns 2 tivkh double data rate control setup to clock (k, k) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.28 0.28 0.28 0.28 ns 2 tdvkh data input setup to clock (k/k) rise 0.28 0.28 0.28 0.28 ns 2 hold times tkhax address hold after k clock rise 0.40 0.40 0.40 0.40 ns tkhix control hold after k clock rise 0.40 0.40 0.40 0.40 ns tkhix double data rate control hold after clock (k/k) rise (bws 0 , bws 1 , bws 2 , bws 3 ) 0.28 0.28 0.28 0.28 ns tkhdx data input hold after clock (k/k) rise 0.28 0.28 0.28 0.28 ns output times tchqv k/k clock rise to data valid 0.45 0.45 0.45 0.45 ns 1 tchqx data output hold after output k/k clock rise (active to active) -0.45 -0.45 -0.45 -0.45 ns 1 tchcqv k/k clock rise to echo clock valid 0.45 0.45 0.45 0.45 ns tchcqx echo clock hold after k/k clock rise -0.45 -0.45 -0.45 -0.45 ns tcqhqv echo clock high to data valid 0.20 0.20 0.20 0.20 ns 1 tcqhqx echo clock high to data invalid -0.20 -0.20 -0.20 -0.20 ns 1 tchqz clock (k/k) rise to high-z (active to high-z) 0.45 0.45 0.45 0.45 ns 1 tchqx1 clock (k/k) rise to low-z -0.45 -0.45 -0.45 -0.45 ns 1 dll timing tkc var clock phase jitter 0.20 0.20 0.20 0.20 ns tkc lock dll lock time (k) 2048 2048 2048 cycles tdofflowtoreset doff low period to dll reset 5 5 5 ns notes: 1. see ac test loading on page 14. 2. during normal operation, vih, vil, trise, and tfall of inputs must be within 20% of vih, vil, trise, and tfall of clock.
16 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq don?t care undefined t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq read, write, and nop timing diagram t khdx t dvkh t khix t ivkh t khkh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 k k ld r/w sa dq cq cq t khdx t dvkh t khix t ivkh t kh kh t klkh t khkh t khkl nop read (burst of 2) 1 2 3 4 4.5 5 6 7 8 9 10 11 12 read (burst of 2) nop nop (note 3) read (burst of 2) write (burst of 2) read (burst of 2) write (burst of 2) read (burst of 2) nop nop a0 a1 a2 a3 a4 a5 k k ld r/w sa dq cq cq t chqv t chqx t chqz t chqv t chqx1 q01 q02 q11 q12 q41 q42 d21 d22 d31 d32 t khkl t avkh t khax t chcqv t chcqx t chcqv t chcqx
integrated silicon solution, inc. 17 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d ieee 1149.1 tap and boundary scan the sram provides a limited set of jtag functions to test the interconnection between sram i/os and printed circuit board traces or other components. there is no multiplexer in the path from i/o pins to the ram core. in conformance with ieee standard 1149.1, the sram contains a tap controller, instruction register, boundary scan register, bypass register, and id register. the tap controller has a standard 16-state machine that resets internally on power-up. therefore, a trst signal is not required. signal list tck: test clock tms: test mode select tdi: test data-in tdo: test data-out jtag dc operating characteristics (t a = 0 to + 70 c) operates with jedec standard 8-5 (1.8v) logic signal levels parameter symbol minimum typical maximum units notes jtag input high voltage v ih1 1.3 ? v dd +0.3 v 1 jtag input low voltage v il1 -0.3 ? 0.5 v 1 jtag output high level v oh1 v dd -0.4 ? v dd v1, 2 jtag output low level v ol1 v ss ?0.4 v1, 3 1. all jtag inputs and outputs are lvttl-compatible. 2. i oh1 -2ma 3. i ol1 +2ma. jtag ac test conditions (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%) parameter symbol conditions units input pulse high level v ih1 1.3 v input pulse low level v il1 0.5 v input rise time t r1 1.0 ns input fall time t f1 1.0 ns input and output timing reference level 0.9 v
18 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d jtag ac characteristics (t a = 0 to + 70 c, v dd = 1.8v -5%, +5%) parameter symbol minimum maximum units notes tck cycle time t thth 20 ? ns tck high pulse width t thtl 7?n s tck low pulse width t tlth 7?n s tms setup t mvth 4?n s tms hold t thmx 4?n s tdi setup t dvth 4?n s tdi hold t thdx 4?n s tck low to valid data t tlov ?7n s1 1. see ac test loading on page 14. jtag timing diagram tck tms tdi tdo t thtl t tlth t thth t thmx t thdx t tlov t mvth t dvth
integrated silicon solution, inc. 19 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d scan register definition register name bit size x18 or x36 instruction 3 bypass 1 id 32 boundary scan 109 id register definition part field bit number and description revision number (31:29) part configuration (28:12) je dec code (11:1) start bit (0) 4 m x 18 000 000100wx0t0q0b0s0 000 101 001 00 1 2 m x 36 000 00010 0wx0t0q0b0s0 000 101 001 00 1 part conf igura tion definition : wx = 11 for x36, 10 for x18 t = 1 for dll, 0 for non-dll q = 1 for quadb2, 0 for ddr-ii, ddr-iip b = 1 for burst of 4, 0 for burst of 2 s = 1 for separate i/0, 0 for common i/o
20 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d list of ieee 1149.1 standard violations 7.2.1.b, e 7.7.1.a-f 10.1.1.b, e 10.7.1.a-d 6.1.1.d instruction set code instruction tdo output notes 000 extest boundary scan register 2,6 001 idcode 32-bit identification register 010 sample-z boundary scan register 1, 2 011 private do not use 5 100 sample boundary scan register 4 101 private do not use 5 110 private do not use 5 111 bypass bypass register 3 1. places qs in high-z in order to sample all input data, regardless of other sram inputs. 2. tdi is sampled as an input to the first id register to allow for the serial shift of the external tdi data. 3. bypass register is initiated to v ss when bypass instruction is invoked. the bypass register also holds the last serially loaded tdi when exiting the shift-dr state. 4. sample instruction does not place dqs in high-z. 5. this instruction is reser v ed. i n voking this instruction will cause improper sram functionalit y. 6. this extest is not ieee 1149.1-compliant. by default, it places q in high-z. if the internal register on the scan chain is se t high, q will be updated with information loaded via a previous sample instruction. the actual transfer occurs during the update ir state after extest is loaded. the value of the internal register can be changed during sample and extest only. jtag block diagram bypass register (1 bit) identification register (32 bits) instruction register (3 bits) tap controller cont rol signals tdi tms tck tdo
integrated silicon solution, inc. 21 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams i 3 d tap controller state machine test logic reset run test idle select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir e xit2 ir updat e ir 1 1 1 0 0 0 0 1 0 1 1 0 1 1 1 0 01 1 1 0 1 0 0 0 1 1 0 0 0 0 1
22 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams d i 3 d boundary scan exit order the same length is used for x18 and x36 i/o configuration. order pin id order pin id order pin id 1 6r 37 10d 73 2c 2 6 p 3 79 e 7 43 e 3 6n 39 10c 75 2d 4 7p 40 11d 76 2e 57 n4 19 c7 71 e 67 r4 29 d7 82 f 7 8r 43 11b 79 3f 8 8p 44 11c 80 1g 99 r 4 59 b 8 11 f 10 11p 46 10b 82 3g 11 10p 47 11a 83 2g 12 10n 48 10a 84 1h 13 9p 49 9a 85 1j 14 10m 50 8b 86 2j 15 11n 51 7c 87 3k 16 9m 52 6c 88 3j 17 9n 53 8a 89 2k 18 11l 54 7a 90 1k 19 11m 55 7b 91 2l 20 9l 56 6b 92 3l 21 10l 57 6a 93 1m 22 11k 58 5b 94 1l 23 10k 59 5a 95 3n 24 9j 60 4a 96 3m 25 9k 61 5c 97 1n 26 10j 62 4b 98 2m 27 11j 63 3a 99 3p 28 11h 64 2a 100 2n 29 10g 65 1a 101 2p 30 9g 66 2b 102 1p 31 11f 67 3b 103 3r 32 11g 68 1c 104 4r 33 9f 69 1b 105 4p 34 10f 70 3d 106 5p 35 11e 71 3c 107 5n 36 10e 72 1d 108 5r 109 internal no tes: 1) nc pins as defined on fbga pinouts on page 2 are read as ?don?t cares?. 2) state of internal pin (#109) is loaded via jtag
integrated silicon solution, inc. 23 rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams note : 1. controlling dimension : mm package outline 12/10/2007
24 integrated silicon solution, inc. rev. b 08/11/2010 72 mb (2m x 36 & 4m x 18) ddr-iip (burst of 2) cio synchronous srams ordering informa tion commercial range: 0c to +70c speed order part no. organization package 400 mhz is61ddpb22m36-400m3 2mx36 165 bga is61ddpb22m36-400m3l 2mx36 165 bga, lead-free is61ddpb24m18-400m3 4mx18 165 bga is61ddpb24m18-400m3l 4mx18 165 bga, lead-free 375 mhz is61ddpb22m36-375m3 2mx36 165 bga is61ddpb22m36-375m3l 2mx36 165 bga, lead-free IS61DDPB24M18-375M3 4mx18 165 bga IS61DDPB24M18-375M3l 4mx18 165 bga, lead-free

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